1. Technical Field
Embodiments of the present disclosure generally relate to a semiconductor device, and more particularly, a semiconductor device capable of controlling a bulk voltage.
2. Related Art
An internal circuit included in a semiconductor device includes a plurality of PMOS transistors and a plurality of NMOS transistors. Bulks of the PMOS transistors and the NMOS transistors included in the semiconductor device are designed to be applied with bulk voltages. Bulk voltages are applied to prevent a latch-up phenomenon from occurring and threshold voltages of MOS transistors from unstably varying due to a body effect.
In general, levels of bulk voltages to be applied to PMOS transistors and NMOS transistors exert influences on leakage currents of the PMOS transistors and the NMOS transistors in turned-off states and on operation speeds of the PMOS transistors and the NMOS transistors in turned-on states. That is to say, in the case of an NMOS transistor, an amount of leakage current is decreased and an operation speed is increased as a bulk voltage of a level lower than a voltage of a source terminal is applied. Also, in the case of a PMOS transistor, an amount of leakage current is decreased and an operation speed is increased as a bulk voltage of a level higher than a voltage of a source terminal is applied.
A power-down mode is one of the standby modes of a semiconductor device. The power-down mode is an operation mode in which power is applied but generation of an internal clock is interrupted to reduce power consumption. In order to reduce power consumption in the power-down mode, it is important to limit an amount of leakage current to a minimum. Therefore, in order to reduce power consumption in the power-down mode, it is advantageous to set a bulk voltage of an NMOS transistor to be low and set a bulk voltage of a PMOS transistor to be high.